1. Field of the Invention
The present invention relates to an adhesive composition which is particularly suited for using at a step of die-bonding a semiconductor device (semiconductor chip) on an organic substrate and a lead frame and a step of dicing a silicon wafer and the like and die-bonding a semiconductor chip on an organic substrate and a lead frame, an adhesive sheet having an adhesive layer comprising the above adhesive composition and a production process for a semiconductor device using the above adhesive sheet.
2. Description of the Related Art
A semiconductor wafer of silicon, gallium arsenic or the like is produced in a large size, and this wafer is cut and separated (dicing) into small pieces (IC chips) of devices and then transferred to a mounting step which is a subsequent step. In this case, the semiconductor wafer is subjected to the respective steps of dicing, washing, drying, expanding and picking-up in the state that it is adhered in advance on an adhesive sheet, and then it is transferred to a bonding step which is a subsequent step.
In order to simplify the picking-up step and the bonding step among the above steps, various adhesive sheets for dicing and die-bonding which are provided with both a wafer-fixing function and a die-adhering function are proposed (for examples, patent documents 1 to 4).
Adhesive sheets comprising an adhesive layer comprising a specific composition and a base material are disclosed in the patent documents 1 to 4. The above adhesive layer has a function of fixing a wafer in dicing the wafer, and irradiation thereof with an energy beam reduces an adhesive strength thereof and makes it possible to control the adhesive strength between the adhesive layer and the base material, so that when picking up the chip after finishing dicing, the adhesive layer is peeled off together with the chip. When the IC chip provided with the adhesive layer is mounted on a substrate and heated, an adhesive strength of a thermosetting resin contained in the adhesive layer is revealed to complete adhesion between the IC chip and the substrate.
The adhesive sheets disclosed in the patent documents described above enables so-called direct die-bonding and makes it possible to omit a step of applying an adhesive for adhering a die. The adhesives disclosed in the patent documents described above are blended with an energy beam-curable compound having a low molecular weight as an energy beam-curable component. Irradiation with an energy beam polymerizes and cures the energy beam-curable compound to reduce an adhesive strength thereof and makes it easy to peel off the adhesive layer from the base material. In the adhesive layer of the adhesive sheet described above, all the components are cured after die-bonding passing through curing by an energy beam and thermal curing, whereby it adheres the chip firmly on the substrate.
On the other hand, very severe physical properties are required to semiconductor devices in recent years. For example, package reliability under severe hot and humid environment is required. However, a reduction in a thickness of a semiconductor chip itself results in a reduction in a strength of the chip, and the package reliability under severe hot and humid environment has not necessarily been satisfactory.
In the adhesives disclosed in the patent documents described above, the energy beam-curable compound having a low molecular weight is used as an energy beam-curable component, and such energy beam-curable compound having a low molecular weight is liable to bring about interfacial breakage under hot and humid environment due to the short shearing strength depending on the blending proportion thereof, the dispersion state or the curing conditions to reduce an adhesive property between the chip and an adherend such as a printed wiring board. This has made it impossible in a certain case to allow a semiconductor package which is becoming severer to satisfy a required level in reliability.
In a surface mounting method carried out in connection of electronic parts in recent years, a surface mounting method in which the whole part of a package is exposed to high temperature of not lower than a melting point of a solder is carried out. In recent years, a mounting temperature is elevated from 240° C. which has so far been carried out to 260° C. due to transfer to a solder containing no lead from the viewpoint of attentions to the environment to increase a stress produced in the inside of a semiconductor package, and the risk of producing package crack is further elevated.
That is, a reduction in a thickness of a semiconductor chip and a rise in a mounting temperature bring about a reduction in a reliability of a package.
Patent document 1: JP-A-1990-32181
Patent document 2: JP-A-1996-239636
Patent document 3: JP-A-1998-8001
Patent document 4: JP-A-2000-17246